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CGO
2004
IEEE
14 years 1 months ago
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan d...
AOSD
2008
ACM
14 years 2 days ago
Edicts: implementing features with flexible binding times
In a software product line, the binding time of a feature is the time at which one decides to include or exclude a feature from a product. Typical binding site implementations are...
Venkat Chakravarthy, John Regehr, Eric Eide
ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
13 years 7 months ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen
HIPEAC
2011
Springer
12 years 9 months ago
TypeCastor: demystify dynamic typing of JavaScript applications
Dynamic typing is a barrier for JavaScript applications to achieve high performance. Compared with statically typed languages, the major overhead of dynamic typing comes from runt...
Shisheng Li, Buqi Cheng, Xiao-Feng Li
VLSID
2002
IEEE
125views VLSI» more  VLSID 2002»
14 years 10 months ago
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
Francisco Barat, Murali Jayapala, Pieter Op de Bee...