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CVPR
1998
IEEE
14 years 9 months ago
Real-Time 2-D Feature Detection on a Reconfigurable Computer
We have designed and implemented a system for real-time detection of 2-D features on a reconfigurable computer based on Field Programmable Gate Arrays (FPGA `s). We envision this ...
Arrigo Benedetti, Pietro Perona
CODES
2005
IEEE
14 years 1 months ago
An architectural level design methodology for embedded face detection
Face detection and recognition research has attracted great attention in recent years. Automatic face detection has great potential in a large array of application areas, includin...
Vida Kianzad, Sankalita Saha, Jason Schlessman, Ga...
DSD
2007
IEEE
164views Hardware» more  DSD 2007»
14 years 1 months ago
An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation
In this paper, we present an efficient hardware architecture for real-time implementation of quarter-pixel accurate variable block size motion estimation for H.264 / MPEG4 Part 10...
Serkan Oktem, Ilker Hamzaoglu
JRTIP
2007
108views more  JRTIP 2007»
13 years 7 months ago
Real-time hardware acceleration of the trace transform
The trace transform is a novel algorithm that has been shown to be effective in a number of image recognition tasks. It is a generalisation of the Radon transform that has been wid...
Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y...
ISCAS
2005
IEEE
170views Hardware» more  ISCAS 2005»
14 years 1 months ago
Quantized LDPC decoder design for binary symmetric channels
Abstract— Binary Symmetric Channels (BSC) like the Interchip buses and the Intra-chip buses are gaining a lot of attention due to their widespread use with multimedia storage dev...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra