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JSA
2010
158views more  JSA 2010»
13 years 2 months ago
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...
ICC
2011
IEEE
237views Communications» more  ICC 2011»
12 years 7 months ago
Reorganized and Compact DFA for Efficient Regular Expression Matching
—Regular expression matching has become a critical yet challenging technique in content-aware network processing, such as application identification and deep inspection. To meet ...
Kai Wang, Yaxuan Qi, Yibo Xue, Jun Li
ISCAS
2007
IEEE
161views Hardware» more  ISCAS 2007»
14 years 1 months ago
Hardware Architecture of a Parallel Pattern Matching Engine
Abstract— Several network security and QoS applications require detecting multiple string matches in the packet payload by comparing it against predefined pattern set. This proc...
Meeta Yadav, Ashwini Venkatachaliah, Paul D. Franz...
IVC
2008
101views more  IVC 2008»
13 years 7 months ago
A system for processing handwritten bank checks automatically
In the US and many other countries, bank checks are preprinted with the account number and the check number in MICR ink and format; as such, these two numeric fields can be easily...
Rafael Palacios, Amar Gupta
ANCS
2007
ACM
13 years 11 months ago
Compiling PCRE to FPGA for accelerating SNORT IDS
Deep Payload Inspection systems like SNORT and BRO utilize regular expression for their rules due to their high expressibility and compactness. The SNORT IDS system uses the PCRE ...
Abhishek Mitra, Walid A. Najjar, Laxmi N. Bhuyan