363 search results - page 32 / 73 » FPGA interconnect design using logical effort |
FPGA
2008
ACM
13 years 10 months ago
2008
ACM
This paper presents a new technology mapper, WireMap. The mapper uses an edge flow heuristic to improve the routability of a mapped design. The heuristic is applied during the ite...
ICCAD
1995
IEEE
14 years 10 days ago
1995
IEEE
Abstract—We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematical...
ICCAD
1991
IEEE
14 years 9 days ago
1991
IEEE
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
FPL
2007
Springer
14 years 2 months ago
2007
Springer
This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific informatio...
FPGA
1998
ACM
14 years 1 months ago
1998
ACM
In this paper, we developed Boolean matching techniques for complex programmable logic blocks (PLBs) in LUT-based FPGAs. A complex PLB can not only be used as a K-input LUT, but a...