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» FPGA interconnect design using logical effort
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FPGA
2004
ACM
120views FPGA» more  FPGA 2004»
14 years 2 months ago
Flexibility measurement of domain-specific reconfigurable hardware
Traditional metrics used to compare hardware designs include area, performance, and power. However, these metrics do not form a complete evaluation of reconfigurable hardware. For...
Katherine Compton, Scott Hauck
IPPS
2005
IEEE
14 years 2 months ago
Programming Configurable Multiprocessors
A new high performance computation technique involving multiple processors on a single silicon die is quickly gaining popularity. This new design approach provides very high perfo...
Steven A. Guccione
DSD
2009
IEEE
152views Hardware» more  DSD 2009»
14 years 20 days ago
ARROW - A Generic Hardware Fault Injection Tool for NoCs
Todays NoCs are reaching a level where it is getting very hard to ensure 100% of functionality. Consequently, fault tolerance has become an important aspect in todays design techn...
Michael Birner, Thomas Handl
BCS
2008
13 years 10 months ago
A Customisable Multiprocessor for Application-Optimised Inductive Logic Programming
This paper describes a customisable processor designed to accelerate execution of inductive logic programming, targeting advanced field-programmable gate array (FPGA) technology. ...
Andreas Fidjeland, Wayne Luk, Stephen Muggleton
GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
14 years 2 months ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach