363 search results - page 41 / 73 » FPGA interconnect design using logical effort |
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
CADE
2004
Springer
14 years 9 months ago
2004
Springer
Interactive theorem provers can model complex systems, but require much effort to prove theorems. Resolution theorem provers are automatic and powerful, but they are designed to be...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-OnChip (NoC) provide a structured way of realizing interconnections on silic...
ISCAS
2005
IEEE
14 years 2 months ago
2005
IEEE
— Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon...
CASES
2010
ACM
13 years 6 months ago
2010
ACM
Physical Unclonable Functions (PUFs) based on Ring Oscillators (ROs) are a promising primitive for FPGA security. However, the quality of their implementation depends on several d...