363 search results - page 42 / 73 » FPGA interconnect design using logical effort |
146
Voted
MEMOCODE
2003
IEEE
15 years 8 months ago
2003
IEEE
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...
126
Voted
FPL
2009
Springer
15 years 8 months ago
2009
Springer
The creation and optimization of FPGA accelerators comprising several compute cores and memories are challenging tasks in high performance reconfigurable computing. In this paper...
175
Voted
FPGA
2010
ACM
15 years 3 months ago
2010
ACM
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
129
Voted
CL
2000
Springer
15 years 7 months ago
2000
Springer
This paper reports on the design and implementation of FLORA -- a powerful DOOD system that incorporates the features of F-logic, HiLog, and Transaction Logic. FLORA is implemented...
135
Voted
DAC
2012
ACM
13 years 6 months ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...