363 search results - page 46 / 73 » FPGA interconnect design using logical effort |
EH
1999
IEEE
1999
IEEE
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints
14 years 1 months ago
Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraint...
Lecture Notes
Driven by recent innovations in Field-Programmable Gate Arrays (FPGAs), reconfigurable computing offers unique ways to accelerate key algorithms. FPGAs offer a programmable logic f...
DSD
2007
IEEE
14 years 3 months ago
2007
IEEE
An address generator produces a unique address from 1 to k for the input that matches to one of k registered vectors, and produces 0 for other inputs. This paper presents the supe...
CAISE
2003
Springer
14 years 2 months ago
2003
Springer
Extraction-Transformation-Loading (ETL) tools are pieces of software responsible for the extraction of data from several sources, their cleansing, customization and insertion into ...
GLVLSI
2007
IEEE
14 years 3 months ago
2007
IEEE
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...