363 search results - page 59 / 73 » FPGA interconnect design using logical effort |
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
In some cases, minimum Sum-Of-Products (SOP) expressions of Boolean functions can be derived by detecting decomposition and observing the functional properties such as unateness, ...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
In a realistic design flow, circuit and system optimizations must interact with physical aspects of the design. For example, improvements in timing and power may require replacing ...
EMSOFT
2001
Springer
14 years 1 days ago
2001
Springer
Abstract. We classify component-based models of computation into component models and interface models. A component model speci es for each component how the component behaves in a...
FPL
2005
Springer
14 years 1 months ago
2005
Springer
String pattern matching is a computationally expensive task, and when implemented in hardware, it can consume a large amount of resources for processing and storage. This paper pr...