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» FPGA interconnect design using logical effort
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DAC
2005
ACM
14 years 8 months ago
Hardware speech recognition for user interfaces in low cost, low power devices
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer
SIGSOFT
2011
ACM
13 years 2 months ago
Modeling a distributed intrusion detection system using collaborative building blocks
Developing complex distributed systems is a non-trivial task. It is even more difficult when the systems need to dynamically reconfigure the distributed functionalities or tasks...
Linda Ariani Gunawan, Michael Vogel, Frank Alexand...
IPPS
1997
IEEE
13 years 11 months ago
Nearly Optimal One-To-Many Parallel Routing in Star Networks
Star networks were proposedrecently as an attractive alternative to the well-known hypercube models for interconnection networks. Extensive research has been performed that shows ...
Chi-Chang Chen, Jianer Chen
HPCA
2008
IEEE
14 years 8 months ago
Regional congestion awareness for load balance in networks-on-chip
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
Paul Gratz, Boris Grot, Stephen W. Keckler
ASAP
2007
IEEE
134views Hardware» more  ASAP 2007»
14 years 1 months ago
Real-time FPGA-implementation for blue-sky Detection
Currently, television sets with flat plasma and LCD screens with improved resolutions and better color quality are emerging. To fully utilize their capabilities, lower resolution...
Nhut Thanh Quach, Bahman Zafarifar, Georgi Gaydadj...