87 search results - page 10 / 18 » FPGA power reduction using configurable dual-Vdd |
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
A new high performance computation technique involving multiple processors on a single silicon die is quickly gaining popularity. This new design approach provides very high perfo...
VLSID
2005
IEEE
14 years 7 months ago
2005
IEEE
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Mobile video processing as defined in standards like MPEG-4 and H.263 contains a number of timeconsuming computations that cannot be efficiently executed on current hardware archi...
CAV
2006
Springer
13 years 11 months ago
2006
Springer
This paper addresses the problem of computing symbolically the set of reachable configurations of a linear hybrid automaton. A solution proposed in earlier work consists in explori...
JSA
2010
13 years 2 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...