87 search results - page 13 / 18 » FPGA power reduction using configurable dual-Vdd |
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
SAC
2010
ACM
13 years 7 months ago
2010
ACM
Dynamic configuration techniques such as DVFS (Dynamic Voltage and Frequency Scaling) and turning on/off computers are well known ways to promote energy consumption reduction in w...
ISLPED
2010
ACM
13 years 7 months ago
2010
ACM
Structured ASICs provide an exciting middle ground between FPGA and ASIC design methodologies. Compared to ASIC, structured ASIC based designs require lower non recurring engineer...
ISLPED
2003
ACM
14 years 22 days ago
2003
ACM
We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous a...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
- The use of synthesizable reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such domain-special cores are being used for their flexibility, po...