87 search results - page 6 / 18 » FPGA power reduction using configurable dual-Vdd |
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Multi-context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant ove...
DAGSTUHL
2006
13 years 8 months ago
2006
Dynamic and partial reconfiguration discovers more and more the focus in academic and industrial research. Modern systems in e.g. avionic and automotive applications exploit the p...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
In this paper we propose a hybrid FPGA using nanoscale clusters with an architecture similar to clusters of traditional CMOS FPGAs. The proposed cluster is made of a crossbar of n...
ERSA
2010
13 years 5 months ago
2010
SRAM-based FPGA devices are an attractive option for data processing on space-based platforms, due to high computational capabilities and a lower power envelope than traditional pr...
FCCM
2000
IEEE
13 years 12 months ago
2000
IEEE
Although run-time reconfigurable systems have been shown to achieve very high performance, the speedups over traditional microprocessor systems are limited by the cost of configur...