428 search results - page 78 / 86 » FPGA-Based SAT Solver |
TABLEAUX
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. Model checking is a technique for verifying that a finite-state concurrent system is correct with respect to its specification. In bounded model checking (BMC), the sys...
TACAS
2007
Springer
14 years 1 months ago
2007
Springer
ion Randal E. Bryant1 , Daniel Kroening2 , Jo¨el Ouaknine3 , Sanjit A. Seshia4 , Ofer Strichman5 , and Bryan Brady4 1 Carnegie Mellon University, Pittsburgh 2 ETH Z¨urich 3 Oxfor...
SMA
2006
ACM
14 years 1 months ago
2006
ACM
Parametric and feature-based CAD models can be considered to represent families of similar objects. In current modelling systems, however, the semantics of such families are uncle...
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing pro...
FROCOS
2005
Springer
14 years 1 months ago
2005
Springer
We describe results and status of a sub project of the Verisoft [1] project. While the Verisoft project aims at verification of a complete computer system starting with hardware a...