VTS 2005 - PDF Preprint Papers

VTS 2005 IEEE VLSI Test Symposium

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VTS
2005
IEEE

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Data Retention Fault in SRAM Memories: Analysis and Detection Procedures

14 years 5 months ago

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Luigi Dilillo, Patrick Girard, Serge Pravossoudovi...

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Id	Views	Title	Status

1	178	Data Retention Fault in SRAM Memories: Analysis and Detection Procedures	claim
2	162	Low-Cost Alternate EVM Test for Wireless Receiver Systems	claim
3	151	A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers	claim
4	145	Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements	claim
5	116	Closed-Form Simulation and Robustness Models for SEU-Tolerant Design	claim
6	106	Segmented Addressable Scan Architecture	claim
7	102	Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance	claim
8	102	An Efficient Random Jitter Measurement Technique Using Fast Comparator Sampling	claim
9	101	On-Chip Spectrum Analyzer for Analog Built-In Self Test	claim
10	97	Static Compaction of Delay Tests Considering Power Supply Noise	claim
11	96	Implementing a Scheme for External Deterministic Self-Test	claim
12	96	Pseudo-Functional Scan-based BIST for Delay Fault	claim
13	96	Effective TARO Pattern Generation	claim
14	95	SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms	claim
15	90	Soft Error Mitigation for SRAM-Based FPGAs	claim
16	89	Synthesis of Low Power CED Circuits Based on Parity Codes	claim
17	84	Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies	claim

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