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ISCAS
2006
IEEE
107views Hardware» more  ISCAS 2006»
15 years 8 months ago
A versatile computation module for adaptable multimedia processors
—This paper describes a low cost, low power, versatile computation module that can be used as a coarse-grain building block in multimedia processors. The module, which has a data...
Yunan Xiang, R. Pettibon, Martin Margala
MVA
1992
143views Computer Vision» more  MVA 1992»
15 years 3 months ago
A Real-Time Vision System Using Integrated Memory Array Processor Prototype LSI
This study reports on the performance of a Real-Time Vision System (RVS) and its use of an IMAP prototype LSI. This LSI integrates eight 8 bit processors and a 144 Kbit SRAM on a ...
Yoshihiro Fujita, Nobuyuki Yamashita, Shin'ichiro ...
FPL
2005
Springer
125views Hardware» more  FPL 2005»
15 years 8 months ago
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor
This paper describes novel data-path architecture for FPGA-based multimedia processors. The proposed circuit can adapt itself at run-time to different operations and data wordleng...
Marco Lanuzza, Stefania Perri, Martin Margala, Pas...
INTENSIVE
2009
IEEE
15 years 9 months ago
Accelerating K-Means on the Graphics Processor via CUDA
In this paper an optimized k-means implementation on the graphics processing unit (GPU) is presented. NVIDIA’s Compute Unified Device Architecture (CUDA), available from the G8...
Mario Zechner, Michael Granitzer
FCCM
2005
IEEE
102views VLSI» more  FCCM 2005»
15 years 8 months ago
A Signature Match Processor Architecture for Network Intrusion Detection
In this paper, we introduce a novel architecture for a hardware based network intrusion detection system (NIDS). NIDSs are becoming critical components of the network infrastructu...
Janardhan Singaraju, Long Bu, John A. Chandy