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» Factoring large numbers with programmable hardware
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ASPDAC
2001
ACM
68views Hardware» more  ASPDAC 2001»
13 years 11 months ago
Reducing bus delay in submicron technology using coding
ct,. In this paper we study the delay associated with transmission of data through busses. Previous work in this area has presented models for delay assuming a distributed wire mqd...
Paul-Peter Sotiriadis, Anantha Chandrakasan
CHARME
2005
Springer
145views Hardware» more  CHARME 2005»
13 years 9 months ago
Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies
Abstract. Automatic formal verification techniques generally require exponential resources with respect to the number of primary inputs of a netlist. In this paper, we present sev...
Jason Baumgartner, Hari Mony
CORR
2007
Springer
114views Education» more  CORR 2007»
13 years 7 months ago
High Performance Direct Gravitational N-body Simulations on Graphics Processing Units
We present the results of gravitational direct N-body simulations using the commercial graphics processing units (GPU) NVIDIA Quadro FX1400 and GeForce 8800GTX, and compare the re...
Simon Portegies Zwart, Robert G. Belleman, Peter G...
ICSE
2005
IEEE-ACM
14 years 7 months ago
Predictors of customer perceived software quality
Predicting software quality as perceived by a customer may allow an organization to adjust deployment to meet the quality expectations of its customers, to allocate the appropriat...
Audris Mockus, Ping Zhang, Paul Luo Li
MICRO
2008
IEEE
92views Hardware» more  MICRO 2008»
14 years 2 months ago
Online design bug detection: RTL analysis, flexible mechanisms, and evaluation
Higher level of resource integration and the addition of new features in modern multi-processors put a significant pressure on their verification. Although a large amount of res...
Kypros Constantinides, Onur Mutlu, Todd M. Austin