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ISVLSI
2006
IEEE
150views VLSI» more  ISVLSI 2006»
14 years 3 months ago
Design and Analysis of a Low Power VLIW DSP Core
Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...
Chan-Hao Chang, Diana Marculescu
ERSHOV
2003
Springer
14 years 3 months ago
The Translation Power of the Futamura Projections
Despite practical successes with the Futamura projections, it has been an open question whether target programs produced by specializing interpreters can always be as efficient as ...
Robert Glück
ISLPED
2000
ACM
111views Hardware» more  ISLPED 2000»
14 years 2 months ago
Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels
In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Variou...
Khurram Muhammad, Robert B. Staszewski, Poras T. B...
AI
1998
Springer
14 years 2 months ago
Temporally Invariant Junction Tree for Inference in Dynamic Bayesian Network
Abstract. Dynamic Bayesian networks (DBNs) extend Bayesian networks from static domains to dynamic domains. The only known generic method for exact inference in DBNs is based on dy...
Yang Xiang
VISUALIZATION
1997
IEEE
14 years 2 months ago
A topology modifying progressive decimation algorithm
Triangle decimation techniques reduce the number of triangles in a mesh, typically to improve interactive rendering performance or reduce data storage and transmission requirement...
William J. Schroeder