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FPL
2010
Springer
170views Hardware» more  FPL 2010»
13 years 5 months ago
IP Based Configurable SIMD Massively Parallel SoC
Significant advances in the field of configurable computing have enabled parallel processing within a single FieldProgrammable Gate Array (FPGA) chip. This paper presents the imple...
Mouna Baklouti, Mohamed Abid, Philippe Marquet, Je...
ICCAD
2010
IEEE
117views Hardware» more  ICCAD 2010»
13 years 5 months ago
A synthesis flow for digital signal processing with biomolecular reactions
Abstract--We present a methodology for implementing digital signal processing (DSP) operations such as filtering with biomolecular reactions. From a DSP specification, we demonstra...
Hua Jiang, Aleksandra P. Kharam, Marc D. Riedel, K...
ISMVL
2009
IEEE
94views Hardware» more  ISMVL 2009»
14 years 2 months ago
Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions
This paper proposes a design method for floating-point numerical function generators (NFGs) using multi-valued decision diagrams (MDDs). Our method applies to monotone elementary...
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
CAMP
2005
IEEE
14 years 1 months ago
Parallel Extraction Architecture for Image Moments of Numerous Objects
— In this paper, we propose a new architecture that can extract information of numerous objects in an image at highspeed. Various characteristics can be obtained from the image m...
Yoshihiro Watanabe, Takashi Komuro, Shingo Kagami,...
FCCM
2005
IEEE
123views VLSI» more  FCCM 2005»
14 years 1 months ago
A Novel 2D Filter Design Methodology for Heterogeneous Devices
In many image processing applications, fast convolution of an image with a large 2D filter is required. Field Programable Gate Arrays (FPGAs) are often used to achieve this goal ...
Christos-Savvas Bouganis, George A. Constantinides...