Sciweavers

49 search results - page 6 / 10
» Fast buffer insertion considering process variations
Sort
View
ISQED
2002
IEEE
126views Hardware» more  ISQED 2002»
13 years 12 months ago
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-...
FAST
2008
13 years 9 months ago
AWOL: An Adaptive Write Optimizations Layer
Operating system memory managers fail to consider the population of read versus write pages in the buffer pool or outstanding I/O requests when writing dirty pages to disk or netw...
Alexandros Batsakis, Randal C. Burns, Arkady Kanev...
DAC
2007
ACM
14 years 8 months ago
Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction
The ability to account for the growing impacts of multiple process variations in modern technologies is becoming an integral part of nanometer VLSI design. Under the context of ti...
Zhuo Feng, Peng Li, Yaping Zhan
TVLSI
2010
13 years 1 months ago
Variation-Aware System-Level Power Analysis
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
IPL
2007
101views more  IPL 2007»
13 years 7 months ago
Adjacency queries in dynamic sparse graphs
We deal with the problem of maintaining a dynamic graph so that queries of the form “is there an edge between u and v?” are processed fast. We consider graphs of bounded arbor...
Lukasz Kowalik