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FCCM
2004
IEEE
130views VLSI» more  FCCM 2004»
13 years 11 months ago
Hyperreconfigurable Architectures for Fast Run Time Reconfiguration
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit changing needs of a computation during run time. The increasing...
Sebastian Lange, Martin Middendorf
SLIP
2009
ACM
14 years 1 months ago
Floorplan-based FPGA interconnect power estimation in DSP circuits
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic
TVCG
2008
108views more  TVCG 2008»
13 years 7 months ago
Particle-based labeling: Fast point-feature labeling without obscuring other visual features
In many information visualization techniques, labels are an essential part to communicate the visualized data. To preserve the expressiveness of the visual representation, a placed...
Martin Luboschik, Heidrun Schumann, Hilko Cords
MSE
2005
IEEE
137views Hardware» more  MSE 2005»
14 years 29 days ago
Teaching SoC Design in a Project-Oriented Course Based on Robotics
The fast growing complexity and short time-tomarket of embedded systems designs, besides the great increase in capacity of today’s chips, are mobilizing the industry towards to ...
Abner Correa Barros, Pericles Lima, Juliana Xavier...
ASPDAC
2007
ACM
131views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign
Deep submicron effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface d...
Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen