304 search results - page 56 / 61 » Fast power grid simulation |
SBCCI
2005
ACM
14 years 3 months ago
2005
ACM
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer manageme...
EGH
2003
Springer
14 years 3 months ago
2003
Springer
—We present a method for using programmable graphics hardware to solve a variety of boundary value problems. The time-evolution of such problems is frequently governed by partial...
ISSS
2002
IEEE
14 years 2 months ago
2002
IEEE
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
WCNC
2010
IEEE
14 years 1 months ago
2010
IEEE
—In this paper, we propose a new interference alignment (IA) scheme designing jointly the linear transmitter and receiver for the MIMO interference channel system, using minimum ...
SC
2005
ACM
14 years 3 months ago
2005
ACM
The last decade has witnessed a rapid proliferation of superscalar cache-based microprocessors to build high-end computing (HEC) platforms, primarily because of their generality, ...