160 search results - page 2 / 32 » Fast simulation of VLSI interconnects |
IWANN
2007
Springer
14 years 1 months ago
2007
Springer
This paper presents a network architecture to interconnect mixed-signal VLSI1 integrate-and-fire neural networks in a way that the timing of the neural network data is preserved. ...
ICCAD
1996
IEEE
13 years 11 months ago
1996
IEEE
Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However,for typical R...
IPPS
2002
IEEE
14 years 1 days ago
2002
IEEE
Accurate estimation of signal delay is critical to the design and verification of VLSI circuits. At very high frequencies, signal delay in circuits with small feature sizes is do...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
— We present SoCExplore, a framework for fast communicationcentric design space exploration of complex SoCs with networkbased interconnects. Speed-up in exploration is achieved t...
ISCAS
2005
IEEE
14 years 21 days ago
2005
IEEE
— Simulated Evolution (SimE) is a sound stochastic approximation algorithm based on the principles of adaptation. If properly engineered it is possible for SimE to reach nearopti...