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MICRO
2003
IEEE
101views Hardware» more  MICRO 2003»
14 years 3 months ago
Macro-op Scheduling: Relaxing Scheduling Loop Constraints
Ensuring back-to-back execution of dependent instructions in a conventional out-of-order processor requires scheduling logic that wakes up and selects instructions at the same rat...
Ilhyun Kim, Mikko H. Lipasti
IEEEPACT
2002
IEEE
14 years 3 months ago
Cost Effective Memory Dependence Prediction using Speculation Levels and Color Sets
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...
Soner Önder
MICRO
1999
IEEE
123views Hardware» more  MICRO 1999»
14 years 2 months ago
Improving Branch Predictors by Correlating on Data Values
Branch predictors typically use combinations of branch PC bits and branch histories to make predictions. Recent improvements in branch predictors have come from reducing the effec...
Timothy H. Heil, Zak Smith, James E. Smith
LCPC
1998
Springer
14 years 2 months ago
Compiling for SIMD Within a Register
Although SIMD (Single Instruction stream Multiple Data stream) parallel computers have existed for decades, it is only in the past few years that a new version of SIMD has evolved...
Randall J. Fisher, Henry G. Dietz
FPGA
1997
ACM
127views FPGA» more  FPGA 1997»
14 years 2 months ago
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs
We present a general approach to the FPGA technology mapping problem that applies to any logic block composed of lookup tables LUTs and can yield optimal solutions. The connecti...
Amit Chowdhary, John P. Hayes