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ASPDAC
2007
ACM
100views Hardware» more  ASPDAC 2007»
14 years 2 months ago
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong,...
ASIAN
2006
Springer
118views Algorithms» more  ASIAN 2006»
14 years 1 months ago
An Approach to Formal Verification of Arithmetic Functions in Assembly
Abstract. It is customary to write performance-critical parts of arithmetic functions in assembly: this enables finely-tuned algorithms that use specialized processor instructions....
Reynald Affeldt, Nicolas Marti
HPCA
1995
IEEE
14 years 1 months ago
Program Balance and Its Impact on High Performance RISC Architectures
Information on the behavior of programs is essential for deciding the number and nature of functional units in high performance architectures. In this paper, we present studies on...
Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee...
FOCS
1991
IEEE
14 years 1 months ago
On the Exponent of the All Pairs Shortest Path Problem
The upper bound on the exponent, ω, of matrix multiplication over a ring that was three in 1968 has decreased several times and since 1986 it has been 2.376. On the other hand, t...
Noga Alon, Zvi Galil, Oded Margalit
ATS
2005
IEEE
164views Hardware» more  ATS 2005»
14 years 3 days ago
A Family of Logical Fault Models for Reversible Circuits
Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional ...
Ilia Polian, Thomas Fiehn, Bernd Becker, John P. H...