281 search results - page 29 / 57 » Fastpath Speculative Parallelization |
IEEEPACT
2003
IEEE
14 years 3 months ago
2003
IEEE
In Thread-Level Speculation (TLS), speculative tasks generate memory state that cannot simply be combined with the rest of the system because it is unsafe. One way to deal with th...
IEEEPACT
2009
IEEE
14 years 4 months ago
2009
IEEE
Industry is moving towards multi-core designs as we have hit the memory and power walls. Multi-core designs are very effective to exploit thread-level parallelism (TLP) but do not...
IEEEPACT
2007
IEEE
14 years 4 months ago
2007
IEEE
In recent years, microprocessor manufacturers have shifted their focus from single-core to multi-core processors. To avoid burdening programmers with the responsibility of paralle...
ANSS
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper proposes a parallel cycle-accurate microarchitectural simulator which efficiently executes its workload by splitting the simulation process along time-axis into many in...
PPOPP
2010
ACM
14 years 7 months ago
2010
ACM
Drawing inspiration from several previous projects, we present an ownership-record-free software transactional memory (STM) system that combines extremely low overhead with unusua...