281 search results - page 42 / 57 » Fastpath Speculative Parallelization |
MICRO
1999
IEEE
14 years 2 months ago
1999
IEEE
Branch mispredictions are a major obstacle to exploiting instruction-level parallelism, at least in part because all instructions after a mispredicted branch are squashed. However...
EUC
2006
Springer
14 years 1 months ago
2006
Springer
- Modern portable or embedded systems support more and more complex applications. These applications make embedded devices require not only low powerconsumption, but also high comp...
HPCA
2005
IEEE
14 years 3 months ago
2005
IEEE
Chip Multi-Threaded (CMT) processors provide support for many simultaneous hardware threads of execution in various ways, including Simultaneous Multithreading (SMT) and Chip Mult...
ICPADS
2005
IEEE
14 years 3 months ago
2005
IEEE
: Image registration is a technique usually used for aligning two different images taken at different times and/or from different viewing points. A key challenge for medical image ...
VLDB
2005
ACM
14 years 3 months ago
2005
ACM
With the advent of chip multiprocessors, exploiting intra-transaction parallelism is an attractive way of improving transaction performance. However, exploiting intra-transaction ...