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MICRO
2000
IEEE
133views Hardware» more  MICRO 2000»
14 years 2 months ago
Compiler controlled value prediction using branch predictor based confidence
Value prediction breaks data dependencies in a program thereby creating instruction level parallelism that can increase program performance. Hardware based value prediction techni...
Eric Larson, Todd M. Austin
ISCA
1999
IEEE
90views Hardware» more  ISCA 1999»
14 years 2 months ago
Selective Value Prediction
Value Prediction is a relatively new technique to increase instruction-level parallelism by breaking true data dependence chains. A value prediction architecture produces values, ...
Brad Calder, Glenn Reinman, Dean M. Tullsen
CODES
2011
IEEE
12 years 9 months ago
SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs
Two overriding concerns in the development of embedded MPSoCs are ease of programming and hardware complexity. In this paper we present SoC-TM, an integrated HW/SW solution for tr...
Cesare Ferri, Andrea Marongiu, Benjamin Lipton, R....
ICPP
2007
IEEE
14 years 4 months ago
Integrating Memory Compression and Decompression with Coherence Protocols in Distributed Shared Memory Multiprocessors
Ever-increasing memory footprint of applications and increasing mainstream popularity of shared memory parallel computing motivate us to explore memory compression potential in di...
Lakshmana Rao Vittanala, Mainak Chaudhuri
PODC
1999
ACM
14 years 2 months ago
LOTEC: A Simple DSM Consistency Protocol for Nested Object Transactions
In this paper, we describe an e cient software-only Distributed Shared Memory (DSM) consistency protocol for an unconventional but important application domain - object transactio...
Peter C. J. Graham, Yahong Sui