87 search results - page 13 / 18 » Fault Diagnosis Using Timed Automata |
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
SAC
2008
ACM
13 years 7 months ago
2008
ACM
Despite extensive testing in the development phase, residual defects can be a great threat to dependability in the operational phase. This paper studies the utility of lowcost, ge...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Equivalence checking and property checking are powerful techniques to detect error traces. Debugging these traces is a time consuming design task where automation provides help. I...
ATAL
2003
Springer
14 years 28 days ago
2003
Springer
In a large distributed system it is often infeasible or even impossible to perform diagnosis using a single model of the whole system. Instead, several spatially distributed local...
GLVLSI
2008
IEEE
13 years 7 months ago
2008
IEEE
Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported qu...