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» Fault Tolerance for Multistage Interconnection Networks
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SAFECOMP
2007
Springer
14 years 2 months ago
Experimental Evaluation of the DECOS Fault-Tolerant Communication Layer
This paper presents an experimental evaluation of the fault-tolerant communication (FTCOM) layer of the DECOS integrated architecture. The FTCOM layer implements different agreemen...
Jonny Vinter, Henrik Eriksson, Astrit Ademaj, Bern...
FPL
2005
Springer
112views Hardware» more  FPL 2005»
14 years 1 months ago
Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement
Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate ...
Anthony J. Yu, Guy G. Lemieux
HPCA
2007
IEEE
14 years 8 months ago
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
Ricardo Fernández Pascual, José M. G...
TPDS
2008
134views more  TPDS 2008»
13 years 7 months ago
Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On th...
Ricardo Fernández Pascual, José M. G...
ISCAPDCS
2007
13 years 9 months ago
A Node-to-set cluster-fault-tolerant disjoint routing algorithm in pancake graphs
With rapid increase of parallel computation systems in their sizes, it is inevitable to develop algorithms that are applicable even if there exist faulty elements in the systems. ...
Tatsuro Watanabe, Keiichi Kaneko, Shietung Peng