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ITC
1997
IEEE
129views Hardware» more  ITC 1997»
14 years 4 days ago
On Using Machine Learning for Logic BIST
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
Christophe Fagot, Patrick Girard, Christian Landra...
ITC
1999
IEEE
118views Hardware» more  ITC 1999»
14 years 6 days ago
Logic BIST for large industrial designs: real issues and case studies
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K t...
Graham Hetherington, Tony Fryars, Nagesh Tamarapal...
KI
2004
Springer
14 years 1 months ago
Improving Fault Localization of Programs by Using Labeled Dependencies
In this paper we present a new model of Java programs. We show how a program can be compiled into the model. The model can be directly used by a model-based diagnosis engine in ord...
Rong Chen, Daniel Köb, Franz Wotawa
DATE
1999
IEEE
80views Hardware» more  DATE 1999»
14 years 7 days ago
Symmetric Transparent BIST for RAMs
The paper introduces the new concept of symmetric transparent BIST for RAMs. This concept allows to skip the signature prediction phase of conventional transparent BIST approaches...
Sybille Hellebrand, Hans-Joachim Wunderlich, Vyach...
ET
2007
67views more  ET 2007»
13 years 7 months ago
A Formal Analysis of Fault Diagnosis with D-matrices
As new approaches and algorithms are developed for system diagnosis, it is important to reflect on existing approaches to determine their strengths and weaknesses. Of concern is i...
John W. Sheppard, S. G. W. Butcher