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» Fault emulation: a new approach to fault grading
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MSN
2007
Springer
124views Sensor Networks» more  MSN 2007»
14 years 2 months ago
Reducing End-to-End Delay in Multi-path Routing Algorithms for Mobile Ad Hoc Networks
Some of the routing algorithms in mobile ad hoc networks use multiple paths simultaneously. These algorithms can attempt to find nodedisjoint paths to achieve higher fault toleranc...
Nastooh Taheri Javan, Mehdi Dehghan
GRID
2004
Springer
14 years 1 months ago
Checkpoint and Restart for Distributed Components in XCAT3
With the advent of Grid computing, more and more highend computational resources become available for use to a scientist. While this opens up new avenues for scientific research,...
Sriram Krishnan, Dennis Gannon
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
14 years 1 months ago
BISD: Scan-based Built-In self-diagnosis
Abstract—Built-In Self-Test (BIST) is less often applied to random logic than to embedded memories due to the following reasons: Firstly, for a satisfiable fault coverage it may...
Melanie Elm, Hans-Joachim Wunderlich
VLSID
1997
IEEE
98views VLSI» more  VLSID 1997»
14 years 3 days ago
Synthesis for Logical Initializability of Synchronous Finite State Machines
—Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, ) simulator. In practic...
Montek Singh, Steven M. Nowick
EURODAC
1995
IEEE
164views VHDL» more  EURODAC 1995»
13 years 11 months ago
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
Srimat T. Chakradhar, Anand Raghunathan