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» Fault simulation on reconfigurable hardware
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VTS
2003
IEEE
122views Hardware» more  VTS 2003»
14 years 2 months ago
A Reconfigurable Shared Scan-in Architecture
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
Samitha Samaranayake, Emil Gizdarski, Nodari Sitch...
ETS
2007
IEEE
81views Hardware» more  ETS 2007»
14 years 3 months ago
Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips
Dependability is an important attribute for microfluidic biochips that are used for safety-critical applications such as point-of-care health assessment, air-quality monitoring, a...
Tao Xu, Krishnendu Chakrabarty
DATE
2004
IEEE
120views Hardware» more  DATE 2004»
14 years 27 days ago
Evaluation of SystemC Modelling of Reconfigurable Embedded Systems
This paper evaluates the use of pin and cycle accurate SystemC models for embedded system design exploration and early software development. The target system is MicroBlaze Vanill...
Tero Rissa, Adam Donlin, Wayne Luk
FDTC
2006
Springer
117views Cryptology» more  FDTC 2006»
14 years 24 days ago
DPA on Faulty Cryptographic Hardware and Countermeasures
Abstract. Balanced gates are an effective countermeasure against power analysis attacks only if they can be guaranteed to maintain their power balance. Traditional testing and reli...
Konrad J. Kulikowski, Mark G. Karpovsky, Alexander...
JCP
2007
153views more  JCP 2007»
13 years 9 months ago
An Integrated Educational Platform Implementing Real, Remote Lab-Experiments for Electrical Engineering Courses
—This paper describes an Internet-based laboratory, named Remote Monitored and Controlled Laboratory (RMCLab) developed at University of Patras, Greece, for electrical engineerin...
Dimitris Karadimas, Kostas Efstathiou