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» Fault simulation on reconfigurable hardware
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DATE
2005
IEEE
117views Hardware» more  DATE 2005»
14 years 2 months ago
Implicit and Exact Path Delay Fault Grading in Sequential Circuits
1 The first path implicit and exact non–robust path delay fault grading technique for non–scan sequential circuits is presented. Non enumerative exact coverage is obtained, b...
Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, S...
ICES
2001
Springer
91views Hardware» more  ICES 2001»
14 years 1 months ago
Untidy Evolution: Evolving Messy Gates for Fault Tolerance
Abstract. The exploitation of the physical characteristics has already been demonstrated in the intrinsic evolution of electronic circuits. This paper is an initial attempt at crea...
Julian F. Miller, Morten Hartmann
ICECCS
1995
IEEE
108views Hardware» more  ICECCS 1995»
14 years 22 days ago
Using speculative execution for fault tolerance in a real-time system
Achieving fault-tolerance using a primary-backup approach involves overhead of recovery such as activating the backup and propagating execution states, which may a ect the timelin...
Mohamed F. Younis, Grace Tsai, Thomas J. Marlowe, ...
ETS
2006
IEEE
129views Hardware» more  ETS 2006»
14 years 3 months ago
Dynamic Voltage Scaling Aware Delay Fault Testing
The application of Dynamic Voltage Scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faul...
Noohul Basheer Zain Ali, Mark Zwolinski, Bashir M....
ASAP
2006
IEEE
168views Hardware» more  ASAP 2006»
14 years 27 days ago
Dual-Processor Design of Energy Efficient Fault-Tolerant System
A popular approach to guarantee fault tolerance in safety-critical applications is to run the application on two processors. A checkpoint is inserted at the completion of the prim...
Shaoxiong Hua, Pushkin R. Pari, Gang Qu