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» Fault simulation on reconfigurable hardware
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ICSE
2007
IEEE-ACM
14 years 8 months ago
Randomized Differential Testing as a Prelude to Formal Verification
Most flight software testing at the Jet Propulsion Laboratory relies on the use of hand-produced test scenarios and is executed on systems as similar as possible to actual mission...
Alex Groce, Gerard J. Holzmann, Rajeev Joshi
ISLPED
2004
ACM
153views Hardware» more  ISLPED 2004»
14 years 1 months ago
Any-time probabilistic switching model using bayesian networks
Modeling and estimation of switching activities remain to be important problems in low-power design and fault analysis. A probabilistic Bayesian Network based switching model can ...
Shiva Shankar Ramani, Sanjukta Bhanja
MSS
2007
IEEE
82views Hardware» more  MSS 2007»
14 years 2 months ago
Tornado Codes for MAID Archival Storage
This paper examines the application of Tornado Codes, a class of low density parity check (LDPC) erasure codes, to archival storage systems based on massive arrays of idle disks (...
Matthew Woitaszek, Henry M. Tufo
FPGA
2005
ACM
105views FPGA» more  FPGA 2005»
14 years 1 months ago
Soft error rate estimation and mitigation for SRAM-based FPGAs
FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tole...
Ghazanfar Asadi, Mehdi Baradaran Tahoori
MTDT
2003
IEEE
124views Hardware» more  MTDT 2003»
14 years 1 months ago
Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes
Abstract: The high complexity of the faulty behavior observed in DRAMs is caused primarily by the presence of internal floating nodes in defective DRAMs. This paper describes a ne...
Zaid Al-Ars, A. J. van de Goor