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MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
14 years 2 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
IPPS
2007
IEEE
14 years 1 months ago
Implementing and Evaluating Automatic Checkpointing
As the size and popularity of computer clusters go on growing, fault tolerance is becoming a crucial factor to ensure high performance and reliability for applications. To provide...
Antonio S. Martins, Ronaldo Augusto Lara Gon&ccedi...
GLVLSI
2003
IEEE
132views VLSI» more  GLVLSI 2003»
14 years 28 days ago
A highly regular multi-phase reseeding technique for scan-based BIST
In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan c...
Emmanouil Kalligeros, Xrysovalantis Kavousianos, D...
GRID
2003
Springer
14 years 26 days ago
Faults in Grids: Why are they so bad and What can be done about it?
Computational Grids have the potential to become the main execution platform for high performance and distributed applications. However, such systems are extremely complex and pro...
Raissa Medeiros, Walfredo Cirne, Francisco Vilar B...
MOBIHOC
2010
ACM
13 years 5 months ago
Data preservation under spatial failures in sensor networks
In this paper, we address the problem of preserving generated data in a sensor network in case of node failures. We focus on the type of node failures that have explicit spatial s...
Navid Hamed Azimi, Himanshu Gupta, Xiaoxiao Hou, J...