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» Fault-Based Test Case Generation for Component Connectors
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DAC
2012
ACM
11 years 10 months ago
A metric for layout-friendly microarchitecture optimization in high-level synthesis
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
Jason Cong, Bin Liu
KBSE
2007
IEEE
14 years 1 months ago
Improving evolutionary class testing in the presence of non-public methods
Automating the generation of object-oriented unit tests is a challenging task. This is mainly due to the complexity and peculiarities that the principles of object-orientation imp...
Stefan Wappler, Ina Schieferdecker
ICSM
2005
IEEE
14 years 1 months ago
Call Stack Coverage for Test Suite Reduction
Test suite reduction is an important test maintenance activity that attempts to reduce the size of a test suite with respect to some criteria. Emerging trends in software developm...
Scott McMaster, Atif M. Memon
ECAI
2010
Springer
13 years 8 months ago
On Testing Answer-Set Programs
Answer-set programming (ASP) is a well-acknowledged paradigm for declarative problem solving, yet comparably little effort has been spent on the investigation of methods to support...
Tomi Janhunen, Ilkka Niemelä, Johannes Oetsch...
VTS
2003
IEEE
115views Hardware» more  VTS 2003»
14 years 23 days ago
Fault Testing for Reversible Circuits
Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today’s VLSI circuits, if curre...
Ketan N. Patel, John P. Hayes, Igor L. Markov