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DAC
2005
ACM
13 years 9 months ago
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits
Reliability of nanometer circuits is becoming a major concern in today’s VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft erro...
Chong Zhao, Yi Zhao, Sujit Dey
DAC
2000
ACM
14 years 8 months ago
Self-test methodology for at-speed test of crosstalk in chip interconnects
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...
Xiaoliang Bai, Sujit Dey, Janusz Rajski
ICCAD
2007
IEEE
107views Hardware» more  ICCAD 2007»
14 years 4 months ago
Computation of minimal counterexamples by using black box techniques and symbolic methods
— Computing counterexamples is a crucial task for error diagnosis and debugging of sequential systems. If an implementation does not fulfill its specification, counterexamples ...
Tobias Nopper, Christoph Scholl, Bernd Becker
CF
2004
ACM
14 years 26 days ago
Designing and testing fault-tolerant techniques for SRAM-based FPGAs
This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable a...
Fernanda Lima Kastensmidt, Gustavo Neuberger, Luig...
HPCA
2006
IEEE
14 years 7 months ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...