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ICCAD
1993
IEEE
111views Hardware» more  ICCAD 1993»
13 years 11 months ago
Unifying synchronous/asynchronous state machine synthesis
We present a design style and synthesis algorithm that encompasses both asynchronous and synchronous state machines. Our proposed design style not only supports generalized “bur...
Kenneth Y. Yun, David L. Dill
SPIN
2000
Springer
13 years 11 months ago
Modeling the ASCB-D Synchronization Algorithm with SPIN: A Case Study
In this paper, we describe our application of SPIN 1 to model an algorithm used to synchronize the clocks of modules that provide periodic real-time communication over a network. W...
Nicholas Weininger, Darren D. Cofer
ISPD
2005
ACM
130views Hardware» more  ISPD 2005»
14 years 1 months ago
Improved algorithms for link-based non-tree clock networks for skew variability reduction
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
Anand Rajaram, David Z. Pan, Jiang Hu
ISCAS
2006
IEEE
106views Hardware» more  ISCAS 2006»
14 years 1 months ago
A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time
—This paper presents a Frequency-Estimation Algorithm for the ADPLL designs instead of traditional binary frequency-search algorithm. With the proposed ADPLL architecture and syn...
Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu
ICCD
1992
IEEE
82views Hardware» more  ICCD 1992»
13 years 11 months ago
A Comparison of Self-Timed Design Using FPGA, CMOS, and GaAs Technologies
Asynchronous or self-timed systems that do not rely on a global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in ...
Erik Brunvand, Nick Michell, Kent F. Smith