229 search results - page 8 / 46 » Fault-Tolerant Clock Synchronization in CAN |
DAC
2011
ACM
12 years 7 months ago
2011
ACM
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
PATMOS
2004
Springer
14 years 1 months ago
2004
Springer
Synchronization between independently clocked regions in a high performance system is often subject to latencies of more than one clock cycle. We show how the latency can be reduce...
ICDCS
2012
IEEE
11 years 10 months ago
2012
IEEE
Today’s largest High Performance Computing (HPC) systems exceed one Petaflops (1015 floating point operations per second) and exascale systems are projected within seven years...
IOLTS
2008
IEEE
14 years 2 months ago
2008
IEEE
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
CCS
2009
ACM
14 years 8 months ago
2009
ACM
In this paper, we re-visit the problem of unconditionally secure message transmission (USMT) from a sender S to a receiver R, who are part of a distributed synchronous network, mo...