22 search results - page 3 / 5 » Fault-tolerant 3D clock network |
DSN
2004
IEEE
14 years 8 days ago
2004
IEEE
Some safety-critical distributed embedded systems may need to use centralized components to achieve certain dependability properties. The difficulty in combining centralized and d...
ASPDAC
2010
ACM
13 years 6 months ago
2010
ACM
INFOCOM
2006
IEEE
14 years 2 months ago
2006
IEEE
— We discuss the evolution of teleconferencing and networked visualization applications to support 3-dimensional display technologies. The implications of a continuation of Moore...
DSN
2006
IEEE
14 years 2 months ago
2006
IEEE
As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Computer architects have typically ad...
GLVLSI
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...