22 search results - page 4 / 5 » Fault-tolerant 3D clock network |
SLIP
2009
ACM
14 years 3 months ago
2009
ACM
This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering l...
WDAG
2007
Springer
14 years 2 months ago
2007
Springer
Consider a distributed network of n nodes that is connected to a global source of “beats”. All nodes receive the “beats” simultaneously, and operate in lock-step. A scheme ...
ISQED
2002
IEEE
14 years 1 months ago
2002
IEEE
This paper presents a methodology for the statistical analysis of clock tree structures. It allows to accurately predict and analyze the impact of process variation on clock skew....
CNSR
2010
IEEE
13 years 12 months ago
2010
IEEE
— Buffered crossbar (CICQ) switches have shown a high potential in scaling Internet routers capacity. However, they require expensive on-chip buffers whose cost grows quadratical...
ISLPED
2004
ACM
14 years 2 months ago
2004
ACM
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...