Sciweavers

163 search results - page 27 / 33
» Features of Future Network Processor Architectures
Sort
View
CISIS
2010
IEEE
14 years 2 months ago
Computational Grid as an Appropriate Infrastructure for Ultra Large Scale Software Intensive Systems
—Ultra large scale (ULS) systems are future software intensive systems that have billions of lines of code, composed of heterogeneous, changing, inconsistent and independent elem...
Babak Rezaei Rad, Fereidoon Shams Aliee
FPL
2005
Springer
112views Hardware» more  FPL 2005»
14 years 1 months ago
Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement
Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate ...
Anthony J. Yu, Guy G. Lemieux
ISPAN
2005
IEEE
14 years 1 months ago
Process Scheduling for the Parallel Desktop
Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power ma...
Eitan Frachtenberg
ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
12 years 11 months ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...
ECRTS
2007
IEEE
14 years 1 months ago
Cache-Aware Timing Analysis of Streaming Applications
Of late, there has been a considerable interest in models, algorithms and methodologies specifically targeted towards designing hardware and software for streaming applications. ...
Samarjit Chakraborty, Tulika Mitra, Abhik Roychoud...