51 search results - page 6 / 11 » Feedback mechanisms for improving probabilistic memory prefe... |
ICS
2001
Tsinghua U.
14 years 2 days ago
2001
Tsinghua U.
We describe the Slice Processor micro-architecture that implements a generalized operation-based prefetching mechanism. Operation-based prefetchers predict the series of operation...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded...
CGO
2004
IEEE
13 years 11 months ago
2004
IEEE
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
HOTOS
2009
IEEE
13 years 11 months ago
2009
IEEE
Flash memory is the largest change to storage in recent history. To date, most research has focused on integrating flash as persistent storage in file systems, with little emphasi...