51 search results - page 9 / 11 » Feedback mechanisms for improving probabilistic memory prefe... |
MSS
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper presents the RAM Enhanced Disk Cache Project, REDCAP, a new cache of disk blocks which reduces the read I/O time by using a small portion of the main memory. The essent...
PLDI
1999
ACM
13 years 11 months ago
1999
ACM
Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency hav...
HPCA
2008
IEEE
14 years 7 months ago
2008
IEEE
Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrongpath (i.e. mis-speculated) instructions. These scheme...
ASPLOS
2008
ACM
13 years 9 months ago
2008
ACM
Memory errors are a notorious source of security vulnerabilities that can lead to service interruptions, information leakage and unauthorized access. Because such errors are also ...
HPCA
2004
IEEE
14 years 7 months ago
2004
IEEE
Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixe...