41 search results - page 2 / 9 » Fetch Directed Instruction Prefetching |
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
Current trends in processor design are pointing to deeper and wider pipelines and superscalar architectures. The efficient use of these resources requires speculative execution, ...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
—L1 instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 instruction caches large enough t...
TPDS
1998
13 years 7 months ago
1998
—Instruction fetching is critical to the performance of a superscalar microprocessor. We develop a mathematical model for three different cache techniques and evaluate its perfor...
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
Previous research has shown that the SPEC benchmarks achieve low miss ratios in relatively small instruction caches. This paper presents evidence that current software-development...