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FPL
2009
Springer
96views Hardware» more  FPL 2009»
14 years 2 months ago
Noise impact of single-event upsets on an FPGA-based digital filter
Field-programmable gate arrays are well-suited to DSP and digital communications applications. SRAM-based FPGAs, however, are susceptible to radiation-induced single-event upsets ...
Brian H. Pratt, Michael J. Wirthlin, Michael P. Ca...
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
14 years 2 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
14 years 2 months ago
CMOS system-on-a-chip voltage scaling beyond 50nm
† The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected loc...
Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoo...
ICCAD
2000
IEEE
104views Hardware» more  ICCAD 2000»
14 years 2 months ago
Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures
— Fault diagnosis has particular importance in the context of field programmable gate arrays (FPGAs) because faults can be avoided by reconfiguration at almost no real cost. Cl...
Ian G. Harris, Russell Tessier
ARITH
2007
IEEE
14 years 1 months ago
Return of the hardware floating-point elementary function
The study of specific hardware circuits for the evaluation of floating-point elementary functions was once an active research area, until it was realized that these functions were...
Jérémie Detrey, Florent de Dinechin,...