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    TC
    2008
    138views Information Technology» more  TC 2008»
    High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware
    13 years 7 months ago
    High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware
    Download  halcyon.usc.edu
    Numerical linear algebra operations are key primitives in scientific computing. Performance optimizations of such operations have been extensively investigated. With the rapid adva...
    Ling Zhuo, Viktor K. Prasanna
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    TIFS
    2008
    142views more  TIFS 2008»
    An FPGA-Based Network Intrusion Detection Architecture
    13 years 7 months ago
    An FPGA-Based Network Intrusion Detection Architecture
    Download  home.engineering.iastate.edu
    Abstract--Network intrusion detection systems (NIDSs) monitor network traffic for suspicious activity and alert the system or network administrator. With the onset of gigabit netwo...
    Abhishek Das, David Nguyen, Joseph Zambreno, Gokha...
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    TODAES
    2008
    158views more  TODAES 2008»
    Designing secure systems on reconfigurable hardware
    13 years 7 months ago
    Designing secure systems on reconfigurable hardware
    Download  cisr.nps.edu
    The extremely high cost of custom ASIC fabrication makes FPGAs an attractive alternative for deployment of custom hardware. Embedded systems based on reconfigurable hardware integ...
    Ted Huffmire, Brett Brotherton, Nick Callegari, Jo...
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    TVLSI
    2008
    133views more  TVLSI 2008»
    A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
    13 years 7 months ago
    A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
    Download  www.eecs.wsu.edu
    Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
    Mitchell J. Myjak, José G. Delgado-Frias
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    TVLSI
    2008
    121views more  TVLSI 2008»
    Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores
    13 years 7 months ago
    Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores
    Download  halcyon.usc.edu
    Recently, it has become possible to implement floating-point cores on field-programmable gate arrays (FPGAs) to provide acceleration for the myriad applications that require high-p...
    Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna
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