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CASES
2006
ACM
13 years 11 months ago
Improving the performance and power efficiency of shared helpers in CMPs
Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. One alterna...
Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi...
IEEEPACT
2008
IEEE
14 years 2 months ago
Multi-optimization power management for chip multiprocessors
The emergence of power as a first-class design constraint has fueled the proposal of a growing number of run-time power optimizations. Many of these optimizations trade-off power...
Ke Meng, Russ Joseph, Robert P. Dick, Li Shang
ISCA
2007
IEEE
113views Hardware» more  ISCA 2007»
14 years 2 months ago
Thermal modeling and management of DRAM memory systems
With increasing speed and power density, high-performance memories, including FB-DIMM (Fully Buffered DIMM) and DDR2 DRAM, now begin to require dynamic thermal management (DTM) a...
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard Da...
INFOCOM
2009
IEEE
14 years 2 months ago
Nuclei: GPU-Accelerated Many-Core Network Coding
—While it is a well known result that network coding achieves optimal flow rates in multicast sessions, its potential for practical use has remained to be a question, due to its...
Hassan Shojania, Baochun Li, Xin Wang
CODES
2007
IEEE
14 years 2 months ago
Three-dimensional multiprocessor system-on-chip thermal optimization
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...
Chong Sun, Li Shang, Robert P. Dick