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ACSD
2003
IEEE
103views Hardware» more  ACSD 2003»
15 years 7 months ago
Design Validation of ZCSP with SPIN
— We consider the problem of specifying a model of the Zero Copy Secured Protocol for the purpose of LTL verification with the SPIN Model Checker. ZCSP is based on Direct Memory...
Vincent Beaudenon, Emmanuelle Encrenaz, Jean Lou D...
CORR
2009
Springer
242views Education» more  CORR 2009»
15 years 10 days ago
Adaptive Scheduling of Data Paths using Uppaal Tiga
Abstract. We apply Uppaal Tiga to automatically compute adaptive scheduling strategies for an industrial case study dealing with a state-of-the-art image processing pipeline of a p...
Israa AlAttili, Fred Houben, Georgeta Igna, Steffe...
ICCAD
2004
IEEE
100views Hardware» more  ICCAD 2004»
15 years 11 months ago
A chip-level electrostatic discharge simulation strategy
This paper presents a chip-level charged device model (CDM) electrostatic discharge (ESD) simulation method. The chip-level simulation is formulated as a DC analysis problem. A ne...
Haifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, S...
125
Voted
FSTTCS
2007
Springer
15 years 8 months ago
Propositional Dynamic Logic for Message-Passing Systems
We examine a bidirectional Propositional Dynamic Logic (PDL) for message sequence charts (MSCs) extending LTL and TLC− . Every formula is translated into an equivalent communicat...
Benedikt Bollig, Dietrich Kuske, Ingmar Meinecke
109
Voted
CONCUR
1998
Springer
15 years 6 months ago
It's About Time: Real-Time Logics Reviewed
Abstract. We summarize and reorganize some of the last decade's research on real-time extensions of temporal logic. Our main focus is on tableau constructions for model checki...
Thomas A. Henzinger